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K9F1608W0A-TCB0, K9F1608W0A-TIB0
Document Title
2M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 1.0 1.1 Initial issue. Data Sheet 1998. Data Sheet 1999. 1) Added CE don' care mode during the data-loading and reading t 1.2 1.3 1) Revised real-time map-out algorithm(refer to technical notes) Changed device name - KM29W16000AT -> K9F1608W0A-TCB0 - KM29W16000AIT -> K9F1608W0A-TIB0 July 23th 1999 Sep.15th 1999 Final Final
Draft Date
April 10th 1998 July 14th 1998 April 10th 1999
Remark
Preliminary Final Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
2M x 8 Bit NAND Flash Memory
FEATURES
* Voltage Supply : 2.7V ~ 5.5V * Organization - Memory Cell Array : (2M + 64K)bit x 8bit - Data Register : (256 + 8)bit x8bit * Automatic Program and Erase - Page Program : (256 + 8)Byte - Block Erase : (4K + 128)Byte - Status Register * 264-Byte Page Read Operation - Random Access : 10s(Max.) - Serial Page Access : 80ns(Min.) * Fast Write Cycle Time - Program time : 250s(typ.) - Block Erase time : 2ms (typ.) * Command/Address/Data Multiplexed I/O port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 1M Program/Erase Cycles - Data Retention : 10 years * Command Register Operation * 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch) - Forward Type
FLASH MEMORY
GENERAL DESCRIPTION
The K9F1608W0A is a 2M(2,097,152)x8bit NAND Flash Memory with a spare 64K(65,536)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 264-byte page in typically 250s and an erase operation can be performed in typically 2ms on a 4K-byte block. Data in the page can be read out at 80ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase system functions, including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9F1608W0A extended reliability of 1,000,000 program/erase cycles by providing either ECC(Error Correction Code) or real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 8bytes of a page combined with the other 256 bytes can be utilized by system-level ECC. The K9F1608W0A is an optimum solution for large nonvolatile storage application such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility.
PIN CONFIGURATION
VSS CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC CE RE R/B GND N.C N.C N.C N.C N.C
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP GND R/B VCC VCCQ VSS N.C Pin Function Data Inputs/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ground Input Ready/Busy output Power(2.7V~5.5V) Output Butter Power(2.7V~5.5V) Ground No Connection
N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 VSS
N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 VCCQ
44(40) TSOP (II) STANDARD TYPE
NOTE : Connect all VCC,VccQ and VSS pins of each device to power supply outputs. Do not leave VCC or VSS disconnected.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
Figure 1. FUNCTIONAL BLOCK DIAGRAM
FLASH MEMORY
A8 - A20
X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
16M + 512K Bit NAND Flash ARRAY (256 + 8)Byte x 8192
A0 - A7
Page Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VccQ Vss I/0 0 Global Buffers I/0 7
CE RE WE
Control Logic & High Voltage Generator
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block(=16 Row) (4K + 128)Byte
16M : 8K Row (=512 Block) 8 bit 256B Column 8B Column
1 Page = 264 Byte 1 Block = 264 B x 16 Pages = (4K + 128) Bytes 1 Device = 264B x 16Pages x 512 Blocks = 16.5 Mbits
Page Register 256Byte 8Byte
I/O 0 ~ I/O 7
I/O 0 1st Cycle 2nd Cycle 3rd Cycle A0 A8 A16
I/O 1 A1 A9 A17
I/O 2 A2 A10 A18
I/O 3 A3 A11 A19
I/O 4 A4 A12 A20
I/O 5 A5 A13 *X
I/O 6 A6 A14 *X
I/O 7 A7 A15 *X Column Address Row Address (Page Address)
NOTE : A12 to A20 : Block Address
* : X can be VIL or VIH.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
PRODUCT INTRODUCTION
FLASH MEMORY
The K9F1608W0A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are located from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1608W0A. The K9F1608W0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1608W0A.
Table 1. COMMAND SETS
Function Sequential Data Input Read 1 Read 2 Read ID Reset Page Program Block Erase Read Status 1st. Cycle 80h 00h 50h 90h FFh 10h 60h 70h 2nd. Cycle D0h O O Acceptable Command during Busy
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
PIN DESCRIPTION
Command Latch Enable(CLE)
FLASH MEMORY
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register. Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to outputs data during read operations. The I/O pins float to high-z when the chip is deselected or the outputs are disabled.
Write Protect (WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and return to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or outputs are disabled.
Power Line(VCC & VCCQ)
The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V tolerant I/O with 5V power supply at VCCQ.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Output Current K9F1608W0A-TCB0 K9F1608W0A-TIB0 TSTG IOS Symbol VIN TBIAS Rating
FLASH MEMORY
Unit V C C mA
-0.6 to +7.0 -10 to +125 -40 to +125 -65 to +150 5
NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F1608W0A-TCB0:TA=0 to 70C, K9F1608W0A-TIB0:TA=-40 to 85C)
Parameter Supply Voltage Supply Voltage Supply Voltage Symbol VCC VCCQ1) VSS Min 2.7 2.7 0 Typ. 0 Max 5.5 5.5 0 Unit V V V
NOTE : 1. Vcc and VccQ pins are separater each other.
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Sequential Read Operating Current Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions tcycle=80ns, CE=VIL, IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to 5.5V VOUT=0 to 5.5V I/O Pins Except I/O Pins Vcc=2.7V ~ 3.6V Min 2.0 2.0 -0.3 2.4 8 Typ 10 10 10 5 10 Max 20 20 20 1 50 10 10 VCCQ+0.3 VCC+0.3 0.6 0.4 Vcc=3.6V ~ 5.5V Min 3.0 3.0 -0.3 2.4 8 Typ 15 15 25 5 10 Max 30 30 40 1 50 10 10 VCCQ+0.5 VCC+0.5 0.8 0.4 mA V A mA Unit
IOL(R/B) VOL=0.4V
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
VALID BLOCK
Parameter Valid Block Number Symbol NVB Min 502 Typ. 508
FLASH MEMORY
Max 512 Unit Blocks
NOTE : 1. The K9F1608W0A may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaranteed though its initial number could be reduced. (Refer to the attached technical notes) 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block
AC TEST CONDITION
(K9F1608W0A-TCB0:TA=0 to 70C, K9F1608W0A-TIB0:TA=-40 to 85C, VCC=2.7V ~ 5.5V unless otherwise noted)
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 1 TTL GATE and CL=50pF(3.0V+/-10%),100pF(3.0V~3.6V) Value Vcc=2.7V ~ 3.6V 0.4V to 2.4V 5ns 0.8V and 2.0V 1 TTL GATE and CL = 100pF Vcc=3.6V ~ 5.5V 0.4V to 3.4V
CAPACITANCE(TA=25C, Vcc=5.0V f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L L X X X X ALE L H L H L L L X X X(1) X CE L L L L L L L X X X H H H X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC(2) Read Mode Mode Command Input Address Input(3clock) Command Input Address Input(3clock)
Write Mode Data Input
Sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by
NOTE : 1. X can be VIL or VIH 2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Symbol tPROG Nop tBERS Min Typ 0.25 2 Max 1.5 10 10 Unit ms cycles ms
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 20 40 20 40 40 20 40 30 20 80 20
FLASH MEMORY
Max Unit ns ns ns ns ns ns ns ns ns ns ns
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay ALE to RE Delay(read ID) CE to RE Delay( ID read) Ready to RE Low WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low Last RE High to Busy(at sequential read) CE High to Ready(in case of interception by CE at read) CE High Hold Time(at the last serial read) (3) RE Low to Status Output CE Low to Status Output RE High to WE Low WE High to RE Low Device Resetting Time(Read/Program/Erase)
(1)
Symbol tR tAR tAR1 tCR tRR tWB tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEH tRSTO tCSTO tRHW tWHR tRST
Min 150 200 200 20 80 5 20 0 250 0 50 -
Max 10 200 45 20 30 200 100+tr(R/B) 45 55 5/10/500
(2)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL. 2. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 3. To break the sequential read cycle, CE must be held high for longer time than tCEH.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
NAND Flash Technical Notes
Invalid Block(s)
FLASH MEMORY
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block(s) is called as the invalid block information. The invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block information is written prior to shipping. Since the
invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update) Invalid Block(s) Table
No
Check "FFH" ?
*
Check "FFH" on the 1st and 2nd page
Yes No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
NAND Flash Technical Notes (Continued)
Error in write or read operation
FLASH MEMORY
Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung minimizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Erase Failure Write Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement or ECC Correction Verify ECC -> ECC Correction
Read
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification operation is not needed. Start Write 00H
Write 80H
Write Address
Write Address
Write Data
Wait for tR Time
Write 10H
Verify Data
No
*
Program Error
Write 70H
Yes Program Completed
SR. 6 = 1 ? or R/B = 1 ? Yes No SR. 0 = 0 ?
No
*
*
Program Error
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
Yes
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60H Write Block Address Write D0H Write 70H
FLASH MEMORY
Read Flow Chart
Start Write 00H Write Address Read Data ECC Generation
SR. 6 = 1 ? or R/B = 1 ? Yes No SR. 0 = 0 ? Yes Erase Completed
No
Reclaim the Error
No
Verify ECC Yes Page Read Completed
*
Erase Error
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
Buffer memory
error occurs
Block A
When the error happens in Block "A", try to write the data into another Block "B" by reloading from an external buffer. Then, prevent further system access to Block "A"(by creating a "invalid block" table or other appropriate scheme.)
Block B
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
System Interface Using CE don' -care. t
FLASH MEMORY
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 256byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 3. Program Operation with CE don' -care. t CLE
CE don'-care t
CE
WE ALE
I/O0~7
80H
Start Add.(3Cycle)
Data Input
Data Input
10H
tCS CE
(Max. 55ns)
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Timing requirements : If CE is is exerted high during sequential data-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 55ns.
Figure 4. Read Operation with CE don' -care. t
CLE
CE don'-care t
CE
RE ALE R/B tR
WE
I/O0~7
00H
Start Add.(3Cycle)
Data Output(sequential)
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
* Command Latch Cycle
FLASH MEMORY
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/O 0 ~ 7
tALH
tDH
Command
* Address Latch Cycle
tCLS CLE
tCS CE
tWC
tWC
tWP WE tWH tALS ALE tDS I/O 0 ~ 7 tDH
tWP tWH
tWP
tALH
tDS
tDH
tDS
tDH
A0~A7
A8~A15
A16~A20
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
* Input Data Latch Cycle
tCLH CLE
FLASH MEMORY
tCH CE
tALS ALE
tWC
tWP WE tDS I/O 0 ~ 7 tWH tDH
tDH
tWP
tWP tDH
tDS
tDS
DIN 0
DIN 1
DIN 255
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC CE tREH tCHZ* tREA RE tCHZ* tREA tREA
I/O 0 ~ 7 tRR R/B
Dout
Dout
Dout
NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
* Status Read Cycle
tCLS CLE tCLS tCS CE tCH tWP WE tCSTO tWHR RE tDS I/O 0 ~ 7 70H tDH tIR tCLH
FLASH MEMORY
tCHZ*
tRSTO
tRHZ* Status Output
READ1 OPERATION(READ ONE PAGE)
CLE tCEH CE tCHZ WE tWB tAR ALE tR RE tRR I/O 0 ~ 7
00h
tCRY
tRC
tRHZ
A0 ~ A7
A8 ~ A15
A16 ~ A20
Dout N
Dout N+1
Dout N+2
Dout N+3

Dout 263
Column Address
Page(Row) Address Busy
tRB
R/B
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
READ1 OPERATION(INTERCEPTED BY CE)
FLASH MEMORY
CLE
CE
WE tWB tAR ALE tR RE tRR I/O 0 ~ 7
00h
tCHZ
tRC
A0 ~ A7
A8 ~ A15
A16 ~ A20
Dout N
Dout N+1
Dout N+2
Dout N+3
Column Address
Page(Row) Address Busy
R/B
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE tWB ALE
tR tAR tRR
I/O 0 ~ 7
50H
A0 ~ A7
A8 ~ A15 A16 ~ A20
Dout 255+M
Dout 255+M+1
RE
Dout 263
R/B M Address
Selected Row
256
8 Start address M
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
SEQUENTIAL ROW READ OPERATION
FLASH MEMORY
CLE
CE
WE
ALE
RE
I/O 0 ~ 7
00H
A0 ~ A7 A8 ~ A15 A16 ~ A20
Dout N
Dout N+1
Dout N+2
Dout 263
Dout 0
Dout 1
Dout 2

Dout 263
R/B
M
Busy
Ready
Busy
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
WE tWB ALE tPROG
RE
Din Din Din 10H 263 N N+1 1 up to 264 Byte Data Program Serial Input Command
I/O
0~7
80H
A0 ~ A7 A8 ~ A15 A16 ~ A20 Page(Row) Address
70H Read Status Command
I/O0
Sequential Data Column Input Command Address
17
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
K9F1608W0A-TCB0, K9F1608W0A-TIB0
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
FLASH MEMORY
CLE
CE
WE tWB ALE tBERS
RE
I/O 0 ~ 7
60H
A8 ~ A15 A16 ~ A20 Block Address
DOH
70H
I/O0
R/B
Auto Block Erase Setup Command
Erase Command
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
RE tREA I/O0~7
90H Read ID Command 00H ECH Maker Code EAH Device Code
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
DEVICE OPERATION
PAGE READ
FLASH MEMORY
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, sequential page read and sequential row read. The random read mode is enabled when the page address is changed. The 264 bytes of data within the selected page are transferred to the data registers in less than 10s(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 80ns cycle time by sequentially pulsing RE with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address(column 264). After the data of last column address is clocked out, the next page is automatically selected for sequential read. Waiting 10s again allows for reading of the page. The sequential row read operation is terminated by bringing CE to high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 256 to 263 may be selectively accessed by writing the Read2 command. Addresses A0 to A2 set the starting address of the spare area while addresses A3 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare eight bytes of each page may be sequentially read. The Read1 command(00H) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation
CLE CE WE ALE R/B RE I/O 0 ~ 7
00H Start Add.(3Cycle) A0 ~ A7 & A8 ~ A20 Data Output(Sequential)
tR
(00H Command)
Seek Time
Data Field
Spare Field
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K9F1608W0A-TCB0, K9F1608W0A-TIB0
Figure 4. Read2 Operation
FLASH MEMORY
CLE CE WE ALE R/B RE I/O 0 ~ 7
50H Start Add.(3Cycle) A0 ~ A2 & A8 ~ A20 (A3 ~ A7 : Don't Care) Data Output(Sequential) Spare Field
Busy(Seek Time)
Seek Time
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation tR R/B I/O0~7 tR
tR
00H
Start Add.(3Cycle) A0 ~ A7 & A8 ~ A20
Data Output 1st
Data Output 2nd (264 Byte)
Data Output Nth (264 Byte)
1st 2nd
Nth
Data Field
Spare Field
20
K9F1608W0A-TCB0, K9F1608W0A-TIB0
Figure 6. Sequential Row Read2 Operation tR R/B I/O0~7 tR
FLASH MEMORY
tR
50H
Start Add.(3Cycle) A0 ~ A2 & A8 ~ A20 (A3 ~ A7 : Don't Care)
Data Output 1st
Data Output 2nd (8Byte)
Data Output Nth (8Byte)
1st 2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis. But it also allows multiple partial page programming of a byte or consecutive bytes up to 264 may be programmed in a single page program cycle. The number of partial page programming operation in the same page without an intervening erase operation must not exceed ten. The addressing may be done in random order in a block. A page program cycle consist of a serial data loading period in which up to 264 bytes of data must be loaded into the device, and nonvolatile programming period in which the loaded data is programmed into the appropriate cell. The sequential data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded. In order to program the bytes in the spare columns of 256 to 263, the pointer should be set to the spare area by writing the Read 2 command(50H) to the command register. The pointer remains in the spare area unless the Read 1 command(00H) is entered to retum to the main area. The Page Program confirm command(10H) initiates the programming process. Writing 10H alone without perviously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Status Register may be read RE and CE low after the Read Status command(70H) is written to it. The CPU can detect the completion of program cycle by monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O0) may be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation tPROG R/B I/O
Pass 0~7 80H Address & Data Input A0 ~ A7 & A8 ~ A20 264 Byte Data 10H 70H I/O0
Fail
21
K9F1608W0A-TCB0, K9F1608W0A-TIB0
BLOCK ERASE
FLASH MEMORY
The Erase operation is done on a block(4K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A12 to A20 is valid while A8 to A11 is ignored. The Erase Confirm command(D0H) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required. When the erase operation is complete, the Write Status Bit(I/O0) may be checked. Figure 8 details the sequence.
Figure 8. Block Erase Operation
R/B I/O 0 ~ 7
tBERS
60H
Address Input(2Cycle) Block Add. : A8 ~ A20
D0H
70H
I/O0
Pass
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00H or 50H) should be given before sequential page read cycle.
Table2. Status Register Definition
SR I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Device Operation Write Protect Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" "0" : Busy "0" : Protected "1" : Ready "1" : Not Protected
22
K9F1608W0A-TCB0, K9F1608W0A-TIB0
READ ID
FLASH MEMORY
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (EAH) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE tCR CE WE tAR1 ALE RE I/O 0 ~ 7 tREA
90H Address. 1 cycle A0 ~ A7 :"0" Dout(ECH) Maker code Dout(EAH) Device code
RESET
The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0H when WP is high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation tRST R/B I/O
0~7
FFH
Table3. Device Status
After Power-up Operation Mode Read 1
After Reset Waiting for next command
23
K9F1608W0A-TCB0, K9F1608W0A-TIB0
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation.
VCC Rp = R/B open drain output VCC(Max.) - VOL(Max.) IOL + IL = Note* 8mA +IL
where IL is the sum of the input currents of all devices tied to the R/B pin.
*Note: K9F1608W0A : 5.1V When Vcc=3.6V~5.5V 3.2V When Vcc=2.7V~3.6V GND Device
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
24
High
K9F1608W0A-TCB0, K9F1608W0A-TIB0
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F
FLASH MEMORY
Unit :mm/Inch
0~8 0.25 TYP 0.010 #44(40) #23(21) 0.45~0.75 0.018~0.030 11.760.20 0.4630.008 10.16 0.400 0.50 0.020 #1 #22(20)
+0.10
0.15 -0.05 0.006 -0.002
+0.004
18.410.10 0.7250.004
1.000.10 0.0390.004
1.20 Max. 0.047
18.81 Max. 0.741
0.10 MAX 0.004 0.05 Min. 0.002
(
0.805 ) 0.032
0.350.10 0.0140.004
0.80 0.0315
25

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